1. Field of the Invention
The present invention relates to an unlanded via process, and more particularly, to a method for forming an unlanded via hole.
2. Description of the Prior Art
The technology of semiconductors is improving daily. To increase the scale of integrated circuits, the technology of multilevel interconnects has been developed. In such an integrated circuit, the patterned conductive material on one interconnect level is electrically insulated from the patterned conductive material on another level by a dielectric layer (e.g., a silicon dioxide layer). This dielectric layer is called inter-metal dielectrics (IMD). For the specific-point contact of two levels, via holes are opened in the dielectrics and filled by an electrical conductor. These structures are often referred to as vias.
In some cases, it is necessary to increase the width of the underlying conductive material to provide the landing of the conductor formed in the via hole. Therefore, the increase in minimum width increases the pitch, and correspondingly decreases the packing density. The pitch described above is the width of an interconnect line and the space required between those lines.
For submicron technology, in order to reduce the pitch and save the area, the unlanded via process was developed. Its use has been suggested to form an unlanded via hole, which could contain the conductor unlanded on the underlying conductive material, instead of the original landing via hole. That is, when the conductor in the via hole connects with the underlying conductive material, it is not necessary that the underlying conductive material contains completely the bottom area of the conductor which is in the via hole. In the conventional process, unlanded via etching is the critical step. It should be optimized between high resistance and via profile loss. Therein, the high resistance is due to insufficient etching shown in FIG. 1. Referring to FIG. 2, the via profile loss is due to too much overetching. This also makes via resistance high and the following process, such as barrier forming, to be out of control.
For the foregoing reasons, there is a need for a method of forming an unlanded via hole which can substantially improve the high resistance and the via profile loss problem which occurrs in an unlanded via etching processes.